The present invention relates to integrated circuits, and more particularly, to a filtering circuit for filtering a logic signal having a duration below a threshold.
In many applications, it is necessary to filter brief parasitic signals that may appear at the input terminals of an electronic device. If the electronic device is unable to process these signals, this could lead to its malfunctioning. This problem relates especially to electrically erasable and programmable memories receiving an external clock signal that sets the frequency of the read and/or write operations. These memories are serial memories connected to a bus I2C, for example.
Memories of this type are designed to operate with a clock frequency that should not exceed a maximum frequency specified by the manufacturer. When operating beyond this frequency, the internal logic circuit that controls the write or read operations can no longer follow the frequency imposed on it, and this may lead to operating errors. Operating errors include the writing of a erroneous piece of data in the memory or the accidental erasure of data.
The input stage of electronic devices such as these include a filtering circuit for filtering signals whose duration has a value below a determined threshold Tf. With such a filtering circuit, it should be possible not only to filter pulse trains comprising pulses with a duration smaller than Tf, but also isolated random pulses with a duration smaller than Tf.
There are known ways of providing RC type lowpass filters having a specific cutoff frequency. However, purely analog filters do not have an attenuation in the vicinity of their cutoff frequency that is sufficient for the efficient elimination of certain parasitic signals, such as isolated or random pulses which may cross the filtering barrier.
Another known approach is digital filtering. However, digital filtering requires means for sampling the signal received at input, and computation means to implement a filtering algorithm. In numerous applications, it is not possible to consider providing sampling and computation means of this kind solely for the purpose of filtering parasitic signals that may be received at an input terminal of an electronic device, given the cost and complexity of these means.
In view of the foregoing background, it is an object of the present invention to provide a method and a device for filtering a variation of a logic signal having a duration with a value below a filtering threshold Tf, especially for the filtering of random or recurrent parasitic pulse trains or isolated parasitic pulses.
Another object of the present invention is that the filtering should not require the intervention of digital computation means.
Yet another object of the present invention is that the filtering should be more efficient than low-pass analog filtering, and that the filtering should not let through parasitic signals whose duration has a value below the filtering threshold.
These and other objects, advantages and features according to the present invention are provided by a hybrid filter combining characteristics of analog circuits and characteristics of digital circuits. The analog circuit characteristics may include the generation of a ramp-shaped signal when a variation of the input signal is detected. The ramp-shaped signal gives a time base used as a reference for the filtering of a brief variation in the input signal. The ramp-shaped signal may be applied to a logic circuit having a switching threshold, the output of which is used to generate the output signal of the filter.
If the variation of the input signal disappears before the ramp has reached the switching threshold of the logic circuit, the ramp is reset and the output of the filter remains unchanged. Conversly, if the ramp reaches the threshold of the logic circuit before the variation in the input signal disappears, the output of the logic circuit changes its value and delivers a signal that copies the variation of the input signal.
More specifically, the present invention provides a filtering circuit for filtering a variation of a logic signal having a duration with a value below a predetermined threshold. The filtering circuit comprises means to deliver a first ramp-shaped signal when the logic signal goes from a first value to a second value, and for bringing the first signal back to its initial value when the logic signal goes from the second value to the first value. The filtering circuit further comprises means to deliver a second ramp-shaped signal when the logic signal goes from the second value to the first value, and for bringing back the second signal to its initial value when the logic signal goes from the first value to the second value.
A first logic circuit and a second logic circuit with a switching threshold, respectively receive the first and second signals at input. A memory is used to deliver an output signal having a first value when the signals delivered by the logic circuits have a first pair of values, and a second value when the signals delivered by the logic circuits have a second pair of values.
According to one embodiment, the memory comprises a first memory flip-flop circuit receiving at its resetting input the output of one of the logic circuits, and at its setting input the output of the other logic circuit. According to another embodiment, the memory comprises a second memory flip-flop circuit receiving an output of the first memory flip-flop circuit at its resetting input, and an inverted output of the first memory flip-flop circuit at its setting input. The output of the second memory flip-flop circuit forms the output of the filtering circuit.
According to another embodiment, the slopes of the ramps of the first and second signals are substantially identical, as are the switching thresholds of the first and second logic circuits. According to another embodiment, the means for delivering first and second signals each comprises a capacitor-charging or capacitor-discharging analog circuit, and a switch to discharge or recharge the capacitor when the first or second signal has to be brought back to its initial value.
According to another embodiment, the analog circuit delivering the first signal receives the inverted logic signal at an input, and the analog circuit delivering the second signal receives the logic signal at an input. According to another embodiment, the analog circuit delivering the first signal receives the output of the second logic circuit at an input, and the analog circuit delivering the second signal receives the output of the first logic circuit at an input.
According to yet another embodiment, the first and second logic circuits have a switching hysteresis, and the first and second circuits may be inverter circuits.
The present invention also relates to an integrated circuit comprising a filtering circuit as described above and configured as a buffer circuit at an input of an integrated circuit receiving an external clock signal.
The present invention also relates to a method for filtering a variation of a logic signal having a duration with a value below a predetermined threshold. The method comprises generating a first substantially ramp-shaped signal in response to a first type of variation of the logic signal, and bringing the first signal back to its initial value when the logic signal has a variation of a second type that is the reverse of the first one. A second substantially ramp-shaped signal may be generated in response to a variation of the second type of logic signal, and the second signal is brought back to its initial value when the logic signal has a variation of the first type.
The method further includes applying the first signal to a first logic circuit having a specified switching threshold, and a second signal to a second logic circuit also having a specified switching threshold. An output signal may be generated with a first logic value when the outputs of the two logic circuits have a first pair of values, and a second logic value when the outputs of the two logic circuits have a second pair of values. This is for keeping the output signal at its current value when the outputs of the two logic circuits have a pair of values different from the first and second pairs of values.